|Paste number 12411:||Looking for a little feedback on this function and its comments|
|When:||13 years, 1 month ago|
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(defun handle-popj-14 () (let ((chain-enable (not (zerop (logand #x04000000 *machine-control-register*))))) (if *micro-instruction-trace* (format t "POPJ-14: to ~A chain enable: ~A need fetch: ~A LC ~A~%" *micro-instruction-pointer* chain-enable *need-fetch* *location-counter*)) ;; The POPJ-14 condition is almost completely undocumented. It is not ;; even mentioned in the TI CPU manual. The only reference I have found ;; thus far is in memo 528, which describes the CADR version, which ;; isn't suficient information when it comes to emulating it on Raven. ;; The behavior of POPJ-14 depends on the need-fetch signal (available ;; to microcode as part of the MCR) and on the chain-enable bit also ;; in the MCR (settable directly under microcode control). ;; If need-fetch is set, the top 25 bits of the location counter are ;; transferred to the VMA and a mapped read cycle is initiated. Next, ;; the location counter is incremented. If chain-enable is not set, ;; the microinstruction address being returned to is modified by oring ;; in the value #b10. If we initiated a read cycle and chain-enable is ;; set, the microinstruction address being returned to is modified by ;; oring in the value #b11. Finally, unless chain-enable was set or a ;; read cycle was not required, we update the need-fetch signal; ;; setting it if the updated location-counter is even, clearing it ;; otherwise. ;; There is a cleverness here (and in the corresponding ISTM case for ;; the DISPATCH instruction). Instructions are stored in memory with ;; the even-offsetted instructions in the low half of the memory word. ;; The need-fetch signal is set when the location-counter is -even-. ;; It turns out that when reading the MIB, the high-half of the word ;; is returned when the location counter is even. This means that the ;; location counter actually points to the instruction -after- the one ;; currently being executed. Presumably this also means that either the ;; macroinstruction handlers start off with a check to see if a memory ;; access failed or there is trap functionality to perform the check ;; in hardware (this is suggested by some of the fields in the MCR). ;; If *need-fetch* is set, start a read cycle. (when *need-fetch* (setf (aref *virtual-memory-address*) (ldb (byte 25 1) *location-counter*)) (start-read)) (incf *location-counter*) (unless chain-enable (setf *micro-instruction-pointer* (logior *micro-instruction-pointer* 2))) (when (and chain-enable (not *need-fetch*)) (setf *micro-instruction-pointer* (logior *micro-instruction-pointer* 3))) (when (or chain-enable (not *need-fetch*)) (setf *need-fetch* (evenp *location-counter*)))))
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